FIG. 11 is a circuit diagram illustrating the structure of a memory cell of a conventional FeRAM. This memory cell is formed of one ferroelectric capacitor FC and one selection transistor Tr connected to the ferroelectric capacitor FC. For example, an n-channel MOSFET is used as the selection transistor Tr. The gate of the selection transistor Tr is connected to a word line WL, and the drain is connected to a bit line BL. The source of the selection transistor Tr is connected to one electrode (storage node) of the ferroelectric capacitor FC. The other electrode (plate) of the ferroelectric capacitor FC is electrically connected to a cell plate line CP via which a cell plate voltage is supplied.
FIG. 12 illustrates a hysteresis curve of a ferroelectric material. A feature of the ferroelectric memory is that even when there is no voltage difference between the plate and the storage node, that is, even when there is no electric field across the ferroelectric material of the capacitor, there can be a residual dielectric polarization (points a and d in FIG. 12) which allows the ferroelectric capacitor to be nonvolatile.
If the voltage between the plate and the node is increased to a high level, that is, if a high-electric field is applied across the ferroelectric material of the capacitor, dielectric polarization (paraelectric property of the ferroelectric material) increases and becomes substantially saturated at points c or f in FIG. 12. If the electric field across the ferroelectric material is reduced to zero from the saturation region, the residual dielectric polarization remains (point a or d in FIG. 12) after the electric field becomes zero.
As can be seen from FIG. 12, the magnitude of the residual dielectric polarization .+-.Pr depends on the voltage difference between the plate and the storage node applied when data is written or rewritten into the memory cell. That is, either one of the residual polarization states .+-.Pr at point a or d can be selected by controlling the direction in which an electric field is applied in the write operation. On the other hand, data can be read using the property that the displacement current, which flows when a pulse is applied, varies depending on the polarization state.
In a precharging cycle, a pair of bit lines is precharged to a ground voltage GND (0 V). During the precharging cycle, a sense amplifier (not shown) is maintained in an inactive state. After that, the bit line is released from the precharged state, and the word line WL is selected. Furthermore, a power supply voltage Vcc is applied to the cell plate CP and the sense amplifier (not shown) is activated.
As a result, the memory cell storing data in a polarization state at point a goes to point f along the hysteresis curve. In this case, a small change in the capacitance of the ferroelectric capacitor FC occurs, and a small voltage appears across the linear capacitor of the bit line BL connected in series with the ferroelectric capacitor FC. As a result, the output voltage is small, that is, low-level data is output.
In the case where the memory cell is in the polarization state d, the memory cell goes to state f and further to state a. In this case, a polarization inversion occurs, and thus a larger amount of charge is output via the bit line when Vcc is applied to the cell plate line CP than is output in the transition from state a. The sense amplifier (not show) performs differential amplification, and thus the voltage on the bit line, that is, the voltage on the storage node electrode also becomes equal to Vcc.
In this case, a large change occurs in the capacitance of the ferroelectric capacitor FC, and a large voltage appears across the linear capacitor of the bit line BL connected in series with the ferroelectric capacitor FC. As a result, a high-level output is obtained.
Thereafter, if the voltage on the cell plate line CP is returned from Vcc to 0 V, the polarization state returns to point a if the initial polarization was at point a, and the polarization state goes to point c if the initial polarization was at point d. In the case where the initial polarization was at point d, the polarization eventually returns to point d from point c when the power supply applied to the cell plate line CP is turned off.
Data is rewritten (written) as follows. In order to rewrite data from polarization state a to polarization state d, Vcc is applied to the bit line BL when Vcc is applied to the cell plate line CP (that is, to the plate electrode). As a result, the polarization state changes in the order a, b, c, and d. On the other hand, when data is to be rewritten from polarization state d to polarization state a, 0 V is applied to the bit line BL. In this case, the polarization state changes in the order d, e, f, and a.
That is, data is written into and read out from the memory cell by changing the voltage on the cell plate line CP connected to the ferroelectric capacitor FC between a high-level voltage and a low-level voltage.
The method of driving a FeRAM memory cell described above is called a cell plate (CP line) driving method. In this driving method, in both writing and reading operations, the voltage of the cell plate line CP is changed in the order 0 V, the power supply voltage Vcc, and 0 V. In this driving method, the voltage difference of the cell plate is substantially maintained at the power supply voltage Vcc, and thus a large enough voltage is applied such as to polarize the ferroelectric material to a sufficient degree.
However, in the conventional method of driving the FeRAM memory cell, it takes a long time to drive the cell plate between 0 V and the power supply voltage Vcc in the read or write operation. Another problem of this method is that large electrical power is consumed when the cell plate is driven between 0V and the power supply voltage Vcc.
In view of the above, it is an object of the present invention to provide a method and an apparatus for driving a FeRAM memory cell in such a manner that a memory cell capacitor of a ferroelectric memory is driven in a novel fashion thereby achieving an increase in the operation speed and a reduction in the power consumption and in such a manner that the memory cell capacitor is polarized to a sufficient degree to write data in a highly reliable fashion.